summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSadeep Madurange <sadeep@asciimx.com>2025-08-17 12:24:12 +0800
committerSadeep Madurange <sadeep@asciimx.com>2025-08-17 12:24:12 +0800
commit8b5f69ea6f3516ac433bdbd98f3d1efe058b5861 (patch)
tree20bf041969115d390efe07501e960db7cd3ad91c
parent768ae230f9f8100715533dab49a3cf49f839d6be (diff)
downloadfpm-door-lock-8b5f69ea6f3516ac433bdbd98f3d1efe058b5861.tar.gz
Restore main loop and add bat check.
-rw-r--r--main.c129
1 files changed, 107 insertions, 22 deletions
diff --git a/main.c b/main.c
index 6967083..5ecccb5 100644
--- a/main.c
+++ b/main.c
@@ -8,6 +8,8 @@
#include "fpm.h"
#include "uart.h"
+#define BATMIN 5300
+
#define SERVO_PIN PB1
#define SERVO_DDR DDRB
@@ -102,21 +104,23 @@ static inline void flash_led(void)
}
}
-static inline void pwr_batchk_on(void)
+static inline void pwron_batchk(void)
{
PWR_PORT &= ~(1 << PWR_BATCHK);
}
-static inline void pwr_batchk_off(void)
+static inline void pwroff_batchk(void)
{
PWR_PORT |= (1 << PWR_BATCHK);
}
-static inline uint16_t getbat(void)
+static void check_bat(void)
{
- uint16_t vbg;
+ char s[5];
+ s[4] = 0;
+ uint16_t vbg, vcc;
- pwr_batchk_on();
+ pwron_batchk();
ADMUX |= (1 << REFS1) | (1 << REFS0);
ADCSRA |= (1 << ADEN) | (1 << ADPS2) | (1 << ADPS1); /* clk: 50-200 kHz */
@@ -132,38 +136,119 @@ static inline uint16_t getbat(void)
vbg = (1100UL * ADC) / 1024;
ADCSRA &= ~(1 << ADEN);
- pwr_batchk_off();
+ pwroff_batchk();
// 56k/10k voltage divider
- return (vbg * 66) / 10;
+ vcc = (vbg * 66) / 10;
+
+ itoa(vcc, s, 10);
+ for (int i = 0; i < 4; i++)
+ uart_send((uint8_t)s[i]);
+ uart_send('\r');
+ uart_send('\n');
+
+ if (vcc < BATMIN)
+ flash_led();
}
int main(void)
{
uint16_t id;
- uart_init();
-
- PWR_DDR |= (1 << PWR_BATCHK);
- pwr_batchk_off();
+ /* disable watchdog timer */
+ cli();
+ wdt_reset();
+ MCUSR &= ~(1 << WDRF);
+ WDTCSR |= (1 << WDCE) | (1 << WDE);
+ WDTCSR = 0x00;
+
+ PWR_DDR |= (1 << PWR_BATCHK) | (1 << PWR_FPM) | (1 << PWR_SERVO);
+ pwroff_batchk();
- /* bat check */
+ uart_init();
+ pwron_fpm();
+ fpm_init();
+
+ /* servo */
+ TCCR1A |= (1 << WGM11);
+ TCCR1B |= (1 << WGM12) | (1 << WGM13);
+ TCCR1B |= (1 << CS11);
+ ICR1 = PWM_TOP;
+ TCCR1A |= (1 << COM1A1);
+ SERVO_DDR |= (1 << SERVO_PIN);
+
+ /* battery check */
LED_DDR |= (1 << LED_PIN);
LED_PORT &= ~(1 << LED_PIN);
- flash_led();
+ /* input ports */
+ INPUT_DDR &= ~((1 << BACK_LOCK_PIN) | (1 << BACK_UNLOCK_PIN) |
+ (1 << FRONT_LOCK_PIN) | (1 << FRONT_UNLOCK_PIN) |
+ (1 << ENROLL_PIN));
- char s[5];
- s[4] = 0;
+ INPUT_PORT |= ((1 << BACK_LOCK_PIN) | (1 << BACK_UNLOCK_PIN) |
+ (1 << FRONT_LOCK_PIN) | (1 << FRONT_UNLOCK_PIN) |
+ (1 << ENROLL_PIN));
+
+ EICRA = 0b00000000;
+ EIMSK = (1 << FPM_UNLOCK_INT);
+
+ PCICR |= (1 << PCIE2);
+ PCMSK2 |= ((1 << FRONT_LOCK_INT) | (1 << ENROLL_INT) |
+ (1 << BACK_LOCK_INT) | (1 << BACK_UNLOCK_INT));
for (;;) {
- id = getbat();
- itoa(id, s, 10);
- for (int i = 0; i < 4; i++)
- uart_send((uint8_t)s[i]);
- uart_send('\r');
- uart_send('\n');
- _delay_ms(1000);
+ check_bat();
+
+ switch(cmd) {
+ case LOCK_FRONT:
+ lock();
+ fpm_led(FLASH, RED, 1);
+ break;
+ case LOCK_BACK:
+ lock();
+ break;
+ case UNLOCK_FRONT:
+ if (fpm_match()) {
+ fpm_led(BREATHE, BLUE, 1);
+ unlock();
+ } else {
+ fpm_led(BREATHE, RED, 1);
+ }
+ break;
+ case UNLOCK_BACK:
+ unlock();
+ fpm_led(FLASH, BLUE, 1);
+ break;
+ case ENROLL:
+ id = fpm_match();
+ if (id == 1 || id == 2) {
+ fpm_led(BREATHE, BLUE, 1);
+ _delay_ms(1000);
+ if (fpm_enroll())
+ fpm_led(BREATHE, BLUE, 1);
+ else
+ fpm_led(BREATHE, RED, 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ cmd = NONE;
+ _delay_ms(500);
+
+ pwroff_fpm();
+ set_sleep_mode(SLEEP_MODE_PWR_DOWN);
+ sleep_enable();
+ sleep_bod_disable();
+ sei();
+ sleep_cpu();
+
+ cli();
+ sleep_disable();
+ pwron_fpm();
+ fpm_init();
}
return 0;